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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_receivecontrol.v] - Rev 354


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Rev Log message Author Age Path
354 Whitespace cleanup olof 3369d 06h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
353 Inherit fixes for bit width of constants from ORPSoC olof 3371d 07h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
352 Removed delayed assignments from rtl code olof 3375d 13h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
346 Updated project location olof 3386d 06h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
338 root 4190d 08h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
335 New directory structure. root 4247d 14h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
272 When control packets were received, they were ignored in some cases. tadejm 6485d 10h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
mohor 6546d 22h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
37 Link in the header changed. mohor 6849d 13h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6945d 15h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7019d 09h /ethmac/trunk/rtl/verilog/eth_receivecontrol.v

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