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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Rev 141


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141 Syntax error fixed. mohor 7259d 00h /ethmac/trunk/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 7259d 00h /ethmac/trunk/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7259d 00h /ethmac/trunk/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7261d 04h /ethmac/trunk/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7375d 09h /ethmac/trunk/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 7430d 06h /ethmac/trunk/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 7439d 09h /ethmac/trunk/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 7440d 09h /ethmac/trunk/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 7441d 12h /ethmac/trunk/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 7442d 02h /ethmac/trunk/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 7444d 06h /ethmac/trunk/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 7464d 12h /ethmac/trunk/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 7513d 08h /ethmac/trunk/rtl/verilog/eth_registers.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 7513d 12h /ethmac/trunk/rtl/verilog/eth_registers.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7560d 14h /ethmac/trunk/rtl/verilog/eth_registers.v
21 Status signals changed, Adress decoding changed, interrupt controller
mohor 7561d 11h /ethmac/trunk/rtl/verilog/eth_registers.v
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
mohor 7585d 08h /ethmac/trunk/rtl/verilog/eth_registers.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7634d 08h /ethmac/trunk/rtl/verilog/eth_registers.v

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