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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Rev 346

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Rev Log message Author Age Path
69 Define missmatch fixed. mohor 8325d 11h /ethmac/trunk/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 8326d 10h /ethmac/trunk/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 8327d 13h /ethmac/trunk/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8328d 04h /ethmac/trunk/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 8330d 07h /ethmac/trunk/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 8350d 14h /ethmac/trunk/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8399d 09h /ethmac/trunk/rtl/verilog/eth_registers.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8399d 14h /ethmac/trunk/rtl/verilog/eth_registers.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8446d 15h /ethmac/trunk/rtl/verilog/eth_registers.v
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8447d 12h /ethmac/trunk/rtl/verilog/eth_registers.v

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