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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Rev 352

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 3459d 05h /ethmac/trunk/rtl/verilog/eth_registers.v
346 Updated project location olof 3469d 22h /ethmac/trunk/rtl/verilog/eth_registers.v
338 root 4274d 00h /ethmac/trunk/rtl/verilog/eth_registers.v
335 New directory structure. root 4331d 05h /ethmac/trunk/rtl/verilog/eth_registers.v
333 Some small fixes + some troubles fixed. igorm 5779d 19h /ethmac/trunk/rtl/verilog/eth_registers.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6109d 00h /ethmac/trunk/rtl/verilog/eth_registers.v
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 6109d 04h /ethmac/trunk/rtl/verilog/eth_registers.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6274d 21h /ethmac/trunk/rtl/verilog/eth_registers.v
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 6482d 23h /ethmac/trunk/rtl/verilog/eth_registers.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6630d 14h /ethmac/trunk/rtl/verilog/eth_registers.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6632d 21h /ethmac/trunk/rtl/verilog/eth_registers.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6637d 21h /ethmac/trunk/rtl/verilog/eth_registers.v
164 Ethernet debug registers removed. mohor 6703d 05h /ethmac/trunk/rtl/verilog/eth_registers.v
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 6708d 21h /ethmac/trunk/rtl/verilog/eth_registers.v
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 6724d 23h /ethmac/trunk/rtl/verilog/eth_registers.v
141 Syntax error fixed. mohor 6727d 17h /ethmac/trunk/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 6727d 17h /ethmac/trunk/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 6727d 17h /ethmac/trunk/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 6729d 21h /ethmac/trunk/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6844d 01h /ethmac/trunk/rtl/verilog/eth_registers.v

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