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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Rev 356

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356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4620d 10h /ethmac/trunk/rtl/verilog/eth_registers.v
354 Whitespace cleanup olof 4620d 11h /ethmac/trunk/rtl/verilog/eth_registers.v
352 Removed delayed assignments from rtl code olof 4626d 19h /ethmac/trunk/rtl/verilog/eth_registers.v
346 Updated project location olof 4637d 11h /ethmac/trunk/rtl/verilog/eth_registers.v
338 root 5441d 14h /ethmac/trunk/rtl/verilog/eth_registers.v
335 New directory structure. root 5498d 19h /ethmac/trunk/rtl/verilog/eth_registers.v
333 Some small fixes + some troubles fixed. igorm 6947d 09h /ethmac/trunk/rtl/verilog/eth_registers.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 7276d 14h /ethmac/trunk/rtl/verilog/eth_registers.v
320 TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. igorm 7276d 17h /ethmac/trunk/rtl/verilog/eth_registers.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7442d 11h /ethmac/trunk/rtl/verilog/eth_registers.v
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.
mohor 7650d 13h /ethmac/trunk/rtl/verilog/eth_registers.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7798d 03h /ethmac/trunk/rtl/verilog/eth_registers.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7800d 11h /ethmac/trunk/rtl/verilog/eth_registers.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7805d 11h /ethmac/trunk/rtl/verilog/eth_registers.v
164 Ethernet debug registers removed. mohor 7870d 19h /ethmac/trunk/rtl/verilog/eth_registers.v
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 7876d 10h /ethmac/trunk/rtl/verilog/eth_registers.v
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 7892d 13h /ethmac/trunk/rtl/verilog/eth_registers.v
141 Syntax error fixed. mohor 7895d 07h /ethmac/trunk/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 7895d 07h /ethmac/trunk/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7895d 07h /ethmac/trunk/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7897d 11h /ethmac/trunk/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8011d 15h /ethmac/trunk/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 8066d 13h /ethmac/trunk/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 8075d 16h /ethmac/trunk/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 8076d 15h /ethmac/trunk/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 8077d 18h /ethmac/trunk/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8078d 09h /ethmac/trunk/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 8080d 12h /ethmac/trunk/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 8100d 19h /ethmac/trunk/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8149d 14h /ethmac/trunk/rtl/verilog/eth_registers.v

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