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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_shiftreg.v] - Rev 352

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Rev Log message Author Age Path
352 Removed delayed assignments from rtl code olof 3459d 05h /ethmac/trunk/rtl/verilog/eth_shiftreg.v
346 Updated project location olof 3469d 22h /ethmac/trunk/rtl/verilog/eth_shiftreg.v
338 root 4274d 00h /ethmac/trunk/rtl/verilog/eth_shiftreg.v
335 New directory structure. root 4331d 05h /ethmac/trunk/rtl/verilog/eth_shiftreg.v
332 Case statement improved for synthesys. igorm 5793d 00h /ethmac/trunk/rtl/verilog/eth_shiftreg.v
131 LinkFail signal was not latching appropriate bit. mohor 6729d 21h /ethmac/trunk/rtl/verilog/eth_shiftreg.v
84 LinkFail signal was not latching appropriate bit. mohor 6894d 18h /ethmac/trunk/rtl/verilog/eth_shiftreg.v
37 Link in the header changed. mohor 6933d 05h /ethmac/trunk/rtl/verilog/eth_shiftreg.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7029d 06h /ethmac/trunk/rtl/verilog/eth_shiftreg.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7103d 01h /ethmac/trunk/rtl/verilog/eth_shiftreg.v

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