URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 330

Rev	Log message	Author	Age	Path
330	Warning fixes.	igorm	6998d 03h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7442d 03h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
306	Lapsus fixed (!we -> ~we).	simons	7443d 01h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7464d 21h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302	mbist signals updated according to newest convention	markom	7491d 08h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297	Artisan ram instance added.	simons	7554d 23h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227	Changed BIST scan signals.	tadejm	7854d 23h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210	BIST added.	mohor	7862d 23h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7879d 21h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7941d 23h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v