OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 358

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4935d 17h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4935d 18h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4935d 19h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
354 Whitespace cleanup olof 4935d 21h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
352 Removed delayed assignments from rtl code olof 4942d 04h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
346 Updated project location olof 4952d 21h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
338 root 5756d 23h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
335 New directory structure. root 5814d 04h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
330 Warning fixes. igorm 7291d 02h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7735d 02h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
306 Lapsus fixed (!we -> ~we). simons 7735d 23h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7757d 20h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302 mbist signals updated according to newest convention markom 7784d 07h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297 Artisan ram instance added. simons 7847d 22h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227 Changed BIST scan signals. tadejm 8147d 21h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210 BIST added. mohor 8155d 22h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 8172d 20h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8234d 22h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.