URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 250

Rev	Log message	Author	Age	Path
111	Master state machine had a bug when switching from master write to master read.	mohor	7954d 08h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	7954d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8021d 22h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8030d 23h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
97	Small typo fixed.	lampret	8056d 16h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8060d 16h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8066d 19h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
90	casex changed with case, fifo reset changed.	mohor	8066d 19h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8076d 16h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8076d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v