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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 264

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Rev Log message Author Age Path
113 RxPointer bug fixed. mohor 7931d 08h /ethmac/trunk/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7931d 22h /ethmac/trunk/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.
mohor 7932d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 7932d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8000d 01h /ethmac/trunk/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8009d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8034d 19h /ethmac/trunk/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8038d 19h /ethmac/trunk/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8044d 22h /ethmac/trunk/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8044d 22h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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