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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 269

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269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7065d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7124d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7124d 21h /ethmac/trunk/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7127d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7133d 01h /ethmac/trunk/rtl/verilog/eth_wishbone.v
229 case changed to casex. mohor 7159d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
227 Changed BIST scan signals. tadejm 7159d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7159d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7163d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7166d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
210 BIST added. mohor 7167d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7196d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7197d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7197d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7199d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7203d 04h /ethmac/trunk/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7224d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7244d 04h /ethmac/trunk/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7246d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7249d 22h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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