URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 269

Rev	Log message	Author	Age	Path
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7946d 08h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	7953d 21h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7954d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	7955d 00h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	7955d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8022d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8031d 15h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
97	Small typo fixed.	lampret	8057d 08h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8061d 08h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8067d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v