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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 352

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229 case changed to casex. mohor 7853d 23h /ethmac/trunk/rtl/verilog/eth_wishbone.v
227 Changed BIST scan signals. tadejm 7854d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7854d 04h /ethmac/trunk/rtl/verilog/eth_wishbone.v
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7858d 04h /ethmac/trunk/rtl/verilog/eth_wishbone.v
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7861d 04h /ethmac/trunk/rtl/verilog/eth_wishbone.v
210 BIST added. mohor 7862d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7891d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7892d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7892d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7894d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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