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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 356

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356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3406d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
355 Import Julius Baxter's verilator hints from ORPSoC olof 3406d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
354 Whitespace cleanup olof 3406d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
352 Removed delayed assignments from rtl code olof 3412d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
349 Make all parameters configurable from top level olof 3422d 01h /ethmac/trunk/rtl/verilog/eth_wishbone.v
346 Updated project location olof 3423d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
338 root 4227d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
335 New directory structure. root 4284d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
333 Some small fixes + some troubles fixed. igorm 5733d 01h /ethmac/trunk/rtl/verilog/eth_wishbone.v
329 Defer indication fixed. igorm 5761d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
323 Accidently deleted line put back. igorm 6058d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6062d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6228d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
302 mbist signals updated according to newest convention markom 6254d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
280 Reset has priority in some flipflops. mohor 6514d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 6514d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
272 When control packets were received, they were ignored in some cases. tadejm 6522d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6523d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 6524d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 6583d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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