URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 356

Rev	Log message	Author	Age	Path
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7819d 16h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7822d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7827d 20h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
229	case changed to casex.	mohor	7853d 21h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
227	Changed BIST scan signals.	tadejm	7854d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7854d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7858d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7861d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
210	BIST added.	mohor	7862d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7891d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v