URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 358

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
358	Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version	olof	4640d 19h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
356	Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure	olof	4640d 21h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
355	Import Julius Baxter's verilator hints from ORPSoC	olof	4640d 22h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
354	Whitespace cleanup	olof	4640d 22h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
352	Removed delayed assignments from rtl code	olof	4647d 06h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
349	Make all parameters configurable from top level	olof	4656d 21h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
346	Updated project location	olof	4657d 23h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
338		root	5462d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
335	New directory structure.	root	5519d 06h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
333	Some small fixes + some troubles fixed.	igorm	6967d 20h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
329	Defer indication fixed.	igorm	6996d 05h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
323	Accidently deleted line put back.	igorm	7293d 06h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7297d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7462d 22h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
302	mbist signals updated according to newest convention	markom	7489d 08h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
280	Reset has priority in some flipflops.	mohor	7749d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
278	A new bug (entered with previous update) fixed. When abort occured sometimes data transmission was blocked.	mohor	7749d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
272	When control packets were received, they were ignored in some cases.	tadejm	7757d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7758d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7759d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7818d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7818d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7820d 23h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7826d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
229	case changed to casex.	mohor	7852d 19h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
227	Changed BIST scan signals.	tadejm	7852d 23h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7853d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7857d 00h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7860d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
210	BIST added.	mohor	7861d 00h	/ethmac/trunk/rtl/verilog/eth_wishbone.v

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 358

Filtering Options