URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 359

Rev	Log message	Author	Age	Path
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7765d 22h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7824d 20h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7825d 08h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7827d 16h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7833d 12h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
229	case changed to casex.	mohor	7859d 13h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
227	Changed BIST scan signals.	tadejm	7859d 17h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7859d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7863d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7866d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v