URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 367

Rev	Log message	Author	Age	Path
272	When control packets were received, they were ignored in some cases.	tadejm	7764d 07h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7765d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7766d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7825d 07h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7825d 19h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7828d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7833d 22h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
229	case changed to casex.	mohor	7860d 00h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
227	Changed BIST scan signals.	tadejm	7860d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7860d 05h	/ethmac/trunk/rtl/verilog/eth_wishbone.v