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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 368

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368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 3744d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 3807d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
360 Added partial implementation of the debug register from ORPSoC olof 3934d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
359 Verilator linting fixes olof 3936d 20h /ethmac/trunk/rtl/verilog/eth_wishbone.v
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3938d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3938d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
355 Import Julius Baxter's verilator hints from ORPSoC olof 3938d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
354 Whitespace cleanup olof 3938d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
352 Removed delayed assignments from rtl code olof 3944d 21h /ethmac/trunk/rtl/verilog/eth_wishbone.v
349 Make all parameters configurable from top level olof 3954d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
346 Updated project location olof 3955d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
338 root 4759d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
335 New directory structure. root 4816d 21h /ethmac/trunk/rtl/verilog/eth_wishbone.v
333 Some small fixes + some troubles fixed. igorm 6265d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
329 Defer indication fixed. igorm 6293d 20h /ethmac/trunk/rtl/verilog/eth_wishbone.v
323 Accidently deleted line put back. igorm 6590d 21h /ethmac/trunk/rtl/verilog/eth_wishbone.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6594d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6760d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
302 mbist signals updated according to newest convention markom 6787d 00h /ethmac/trunk/rtl/verilog/eth_wishbone.v
280 Reset has priority in some flipflops. mohor 7046d 17h /ethmac/trunk/rtl/verilog/eth_wishbone.v
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7046d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
272 When control packets were received, they were ignored in some cases. tadejm 7054d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7055d 19h /ethmac/trunk/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7056d 19h /ethmac/trunk/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7115d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7116d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7118d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7124d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
229 case changed to casex. mohor 7150d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
227 Changed BIST scan signals. tadejm 7150d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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