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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 368

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Rev Log message Author Age Path
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7046d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
272 When control packets were received, they were ignored in some cases. tadejm 7054d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7055d 19h /ethmac/trunk/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7056d 19h /ethmac/trunk/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7115d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7116d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7118d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7124d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
229 case changed to casex. mohor 7150d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
227 Changed BIST scan signals. tadejm 7150d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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