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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 365

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Rev Log message Author Age Path
365 Whitespace cleanup olof 3218d 02h /ethmac/trunk/rtl/verilog/ethmac.v
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3218d 23h /ethmac/trunk/rtl/verilog/ethmac.v
360 Added partial implementation of the debug register from ORPSoC olof 3220d 07h /ethmac/trunk/rtl/verilog/eth_top.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3224d 01h /ethmac/trunk/rtl/verilog/eth_top.v
352 Removed delayed assignments from rtl code olof 3230d 09h /ethmac/trunk/rtl/verilog/eth_top.v
349 Make all parameters configurable from top level olof 3240d 00h /ethmac/trunk/rtl/verilog/eth_top.v
346 Updated project location olof 3241d 02h /ethmac/trunk/rtl/verilog/eth_top.v
338 root 4045d 05h /ethmac/trunk/rtl/verilog/eth_top.v
335 New directory structure. root 4102d 10h /ethmac/trunk/rtl/verilog/eth_top.v
333 Some small fixes + some troubles fixed. igorm 5551d 00h /ethmac/trunk/rtl/verilog/eth_top.v
327 Defer indication fixed. igorm 5579d 09h /ethmac/trunk/rtl/verilog/eth_top.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 5880d 04h /ethmac/trunk/rtl/verilog/eth_top.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6046d 01h /ethmac/trunk/rtl/verilog/eth_top.v
302 mbist signals updated according to newest convention markom 6072d 12h /ethmac/trunk/rtl/verilog/eth_top.v
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 6083d 04h /ethmac/trunk/rtl/verilog/eth_top.v
276 Defer indication changed. tadejm 6332d 06h /ethmac/trunk/rtl/verilog/eth_top.v
272 When control packets were received, they were ignored in some cases. tadejm 6340d 06h /ethmac/trunk/rtl/verilog/eth_top.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6341d 08h /ethmac/trunk/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6401d 18h /ethmac/trunk/rtl/verilog/eth_top.v
255 TPauseRq synchronized to tx_clk. mohor 6402d 20h /ethmac/trunk/rtl/verilog/eth_top.v

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