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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 37

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37 Link in the header changed. mohor 8348d 10h /ethmac/trunk/rtl/verilog/ethmac.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8397d 06h /ethmac/trunk/rtl/verilog/ethmac.v
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8397d 10h /ethmac/trunk/rtl/verilog/ethmac.v
23 Number of addresses (wb_adr_i) minimized. mohor 8444d 10h /ethmac/trunk/rtl/verilog/ethmac.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8444d 12h /ethmac/trunk/rtl/verilog/ethmac.v
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8445d 09h /ethmac/trunk/rtl/verilog/ethmac.v
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8469d 06h /ethmac/trunk/rtl/verilog/ethmac.v
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8509d 07h /ethmac/trunk/rtl/verilog/ethmac.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8518d 06h /ethmac/trunk/rtl/verilog/ethmac.v

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