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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 356

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356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4645d 19h /ethmac/trunk/rtl/verilog/ethmac_defines.v
351 Turn defines into parameters in eth_cop olof 4660d 17h /ethmac/trunk/rtl/verilog/eth_defines.v
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4660d 18h /ethmac/trunk/rtl/verilog/eth_defines.v
346 Updated project location olof 4662d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
338 root 5466d 23h /ethmac/trunk/rtl/verilog/eth_defines.v
335 New directory structure. root 5524d 04h /ethmac/trunk/rtl/verilog/eth_defines.v
330 Warning fixes. igorm 7001d 01h /ethmac/trunk/rtl/verilog/eth_defines.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7467d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
302 mbist signals updated according to newest convention markom 7494d 06h /ethmac/trunk/rtl/verilog/eth_defines.v
297 Artisan ram instance added. simons 7557d 21h /ethmac/trunk/rtl/verilog/eth_defines.v
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7620d 02h /ethmac/trunk/rtl/verilog/eth_defines.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7825d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7830d 00h /ethmac/trunk/rtl/verilog/eth_defines.v
238 Defines fixed to use generic RAM by default. mohor 7843d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
232 fpga define added. mohor 7851d 19h /ethmac/trunk/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7865d 21h /ethmac/trunk/rtl/verilog/eth_defines.v
211 Bist added. mohor 7865d 21h /ethmac/trunk/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7882d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7901d 19h /ethmac/trunk/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.		 mohor 7920d 16h /ethmac/trunk/rtl/verilog/eth_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7922d 18h /ethmac/trunk/rtl/verilog/eth_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7944d 23h /ethmac/trunk/rtl/verilog/eth_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8026d 04h /ethmac/trunk/rtl/verilog/eth_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8035d 05h /ethmac/trunk/rtl/verilog/eth_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8071d 01h /ethmac/trunk/rtl/verilog/eth_defines.v
73 Number of interrupts changed mohor 8091d 22h /ethmac/trunk/rtl/verilog/eth_defines.v
68 Registered trimmed. Unused registers removed. mohor 8102d 00h /ethmac/trunk/rtl/verilog/eth_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8102d 01h /ethmac/trunk/rtl/verilog/eth_defines.v
55 Changed that were lost with last update put back to the file. mohor 8103d 03h /ethmac/trunk/rtl/verilog/eth_defines.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8103d 18h /ethmac/trunk/rtl/verilog/eth_defines.v

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