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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 360


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137 Defines for register width added. mii_rst signal in MIIMODER register
mohor 7214d 12h /ethmac/trunk/rtl/verilog/ethmac_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7216d 15h /ethmac/trunk/rtl/verilog/ethmac_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7238d 19h /ethmac/trunk/rtl/verilog/ethmac_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7320d 00h /ethmac/trunk/rtl/verilog/ethmac_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7329d 01h /ethmac/trunk/rtl/verilog/ethmac_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
mohor 7364d 21h /ethmac/trunk/rtl/verilog/ethmac_defines.v
73 Number of interrupts changed mohor 7385d 18h /ethmac/trunk/rtl/verilog/ethmac_defines.v
68 Registered trimmed. Unused registers removed. mohor 7395d 20h /ethmac/trunk/rtl/verilog/ethmac_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 7395d 21h /ethmac/trunk/rtl/verilog/ethmac_defines.v
55 Changed that were lost with last update put back to the file. mohor 7396d 23h /ethmac/trunk/rtl/verilog/ethmac_defines.v

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