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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 360

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Rev Log message Author Age Path
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.
mohor 8337d 13h /ethmac/trunk/rtl/verilog/ethmac_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 8339d 16h /ethmac/trunk/rtl/verilog/ethmac_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8361d 20h /ethmac/trunk/rtl/verilog/ethmac_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8443d 01h /ethmac/trunk/rtl/verilog/ethmac_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8452d 03h /ethmac/trunk/rtl/verilog/ethmac_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8487d 23h /ethmac/trunk/rtl/verilog/ethmac_defines.v
73 Number of interrupts changed mohor 8508d 19h /ethmac/trunk/rtl/verilog/ethmac_defines.v
68 Registered trimmed. Unused registers removed. mohor 8518d 21h /ethmac/trunk/rtl/verilog/ethmac_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8518d 22h /ethmac/trunk/rtl/verilog/ethmac_defines.v
55 Changed that were lost with last update put back to the file. mohor 8520d 01h /ethmac/trunk/rtl/verilog/ethmac_defines.v

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