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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 367

Rev	Log message	Author	Age	Path
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	7902d 06h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7921d 02h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7923d 05h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7945d 09h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8026d 14h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8035d 15h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8071d 11h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
73	Number of interrupts changed	mohor	8092d 08h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
68	Registered trimmed. Unused registers removed.	mohor	8102d 10h	/ethmac/trunk/rtl/verilog/ethmac_defines.v
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8102d 11h	/ethmac/trunk/rtl/verilog/ethmac_defines.v