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[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 221

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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 8058d 13h /ethmac/trunk/rtl/verilog
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 8061d 13h /ethmac/trunk/rtl/verilog
218 Typo error fixed. (When using Bist) mohor 8061d 15h /ethmac/trunk/rtl/verilog
214 Signals for WISHBONE B3 compliant interface added. mohor 8062d 12h /ethmac/trunk/rtl/verilog
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 8062d 12h /ethmac/trunk/rtl/verilog
212 Minor $display change. mohor 8062d 12h /ethmac/trunk/rtl/verilog
211 Bist added. mohor 8062d 12h /ethmac/trunk/rtl/verilog
210 BIST added. mohor 8062d 13h /ethmac/trunk/rtl/verilog
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 8079d 11h /ethmac/trunk/rtl/verilog
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 8079d 11h /ethmac/trunk/rtl/verilog
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 8082d 12h /ethmac/trunk/rtl/verilog
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 8090d 14h /ethmac/trunk/rtl/verilog
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 8091d 15h /ethmac/trunk/rtl/verilog
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 8092d 15h /ethmac/trunk/rtl/verilog
165 HASH improvement needed. mohor 8092d 18h /ethmac/trunk/rtl/verilog
164 Ethernet debug registers removed. mohor 8092d 18h /ethmac/trunk/rtl/verilog
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 8093d 16h /ethmac/trunk/rtl/verilog
160 error acknowledge cycle termination added to display. mohor 8093d 16h /ethmac/trunk/rtl/verilog
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 8094d 13h /ethmac/trunk/rtl/verilog
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 8098d 10h /ethmac/trunk/rtl/verilog

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