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[/] [ethmac/] [trunk/] [rtl/] [verilog] - Rev 23

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23 Number of addresses (wb_adr_i) minimized. mohor 8304d 08h /ethmac/trunk/rtl/verilog
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8304d 11h /ethmac/trunk/rtl/verilog
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8305d 07h /ethmac/trunk/rtl/verilog
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8329d 04h /ethmac/trunk/rtl/verilog
18 Few little NCSIM warnings fixed. mohor 8342d 05h /ethmac/trunk/rtl/verilog
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8369d 05h /ethmac/trunk/rtl/verilog
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8376d 11h /ethmac/trunk/rtl/verilog
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8378d 05h /ethmac/trunk/rtl/verilog
14 Unconnected signals are now connected. mohor 8382d 10h /ethmac/trunk/rtl/verilog
10 Directory structure changed. Files checked and joind together. mohor 8384d 22h /ethmac/trunk/rtl/verilog

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