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[/] [ethmac/] [trunk/] [sim/] - Rev 360

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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3370d 00h /ethmac/trunk/sim/
338 root 4191d 03h /ethmac/trunk/sim/
335 New directory structure. root 4248d 09h /ethmac/trunk/sim/
319 Latest Ethernet IP core testbench. tadejm 6057d 03h /ethmac/trunk/sim/
311 Update script for running different file list files for different RAM models. tadejm 6169d 06h /ethmac/trunk/sim/
310 More signals. tadejm 6169d 06h /ethmac/trunk/sim/
309 Update file list files for different RAM models with byte select accessing. tadejm 6169d 06h /ethmac/trunk/sim/
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 6169d 06h /ethmac/trunk/sim/
299 Artisan RAMs added. mohor 6276d 07h /ethmac/trunk/sim/
295 Few minor changes. tadejm 6283d 05h /ethmac/trunk/sim/
294 Added path to a file with distributed RAM instances for xilinx. tadejm 6285d 05h /ethmac/trunk/sim/
293 initial. tadejm 6309d 03h /ethmac/trunk/sim/
292 Corrected mistake. tadejm 6309d 03h /ethmac/trunk/sim/
291 initial tadejm 6309d 04h /ethmac/trunk/sim/
290 Additional checking for FAILED tests added - for ATS. tadejm 6309d 05h /ethmac/trunk/sim/
225 Some minor changes. tadejm 6582d 03h /ethmac/trunk/sim/
224 Signals for a wave window in Modelsim. tadejm 6582d 05h /ethmac/trunk/sim/
217 Bist supported. mohor 6589d 05h /ethmac/trunk/sim/
215 Bist supported. mohor 6589d 06h /ethmac/trunk/sim/
208 Virtual Silicon RAMs moved to lib directory tadej 6606d 23h /ethmac/trunk/sim/

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