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[/] [ethmac/] [trunk/] [sim/] [rtl_sim/] - Rev 358

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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4079d 07h /ethmac/trunk/sim/rtl_sim/
338 root 4900d 11h /ethmac/trunk/sim/rtl_sim/
335 New directory structure. root 4957d 16h /ethmac/trunk/sim/rtl_sim/
319 Latest Ethernet IP core testbench. tadejm 6766d 10h /ethmac/trunk/sim/rtl_sim/
311 Update script for running different file list files for different RAM models. tadejm 6878d 13h /ethmac/trunk/sim/rtl_sim/
310 More signals. tadejm 6878d 13h /ethmac/trunk/sim/rtl_sim/
309 Update file list files for different RAM models with byte select accessing. tadejm 6878d 13h /ethmac/trunk/sim/rtl_sim/
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 6878d 13h /ethmac/trunk/sim/rtl_sim/
299 Artisan RAMs added. mohor 6985d 14h /ethmac/trunk/sim/rtl_sim/
295 Few minor changes. tadejm 6992d 12h /ethmac/trunk/sim/rtl_sim/
294 Added path to a file with distributed RAM instances for xilinx. tadejm 6994d 13h /ethmac/trunk/sim/rtl_sim/
293 initial. tadejm 7018d 10h /ethmac/trunk/sim/rtl_sim/
292 Corrected mistake. tadejm 7018d 10h /ethmac/trunk/sim/rtl_sim/
291 initial tadejm 7018d 11h /ethmac/trunk/sim/rtl_sim/
290 Additional checking for FAILED tests added - for ATS. tadejm 7018d 12h /ethmac/trunk/sim/rtl_sim/
225 Some minor changes. tadejm 7291d 10h /ethmac/trunk/sim/rtl_sim/
224 Signals for a wave window in Modelsim. tadejm 7291d 12h /ethmac/trunk/sim/rtl_sim/
217 Bist supported. mohor 7298d 12h /ethmac/trunk/sim/rtl_sim/
215 Bist supported. mohor 7298d 13h /ethmac/trunk/sim/rtl_sim/
208 Virtual Silicon RAMs moved to lib directory tadej 7316d 07h /ethmac/trunk/sim/rtl_sim/
207 Virtual Silicon RAM support fixed tadej 7316d 07h /ethmac/trunk/sim/rtl_sim/
206 Virtual Silicon RAM added to the simulation. mohor 7316d 07h /ethmac/trunk/sim/rtl_sim/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7316d 07h /ethmac/trunk/sim/rtl_sim/
187 _info file added. mohor 7322d 06h /ethmac/trunk/sim/rtl_sim/
186 Macro for testbench (DO file). mohor 7322d 07h /ethmac/trunk/sim/rtl_sim/
185 Directory keeper. mohor 7322d 07h /ethmac/trunk/sim/rtl_sim/
184 Modelsim simulation environment should be ready now. mohor 7322d 07h /ethmac/trunk/sim/rtl_sim/
183 Modelsim environment added. mohor 7322d 08h /ethmac/trunk/sim/rtl_sim/
176 lists changed to new directory structure mohor 7326d 13h /ethmac/trunk/sim/rtl_sim/
175 Script fixed to new dir structure mohor 7326d 13h /ethmac/trunk/sim/rtl_sim/

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