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[/] [ethmac/] [trunk/] [sim/] [rtl_sim/] [ncsim_sim/] - Rev 356

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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4027d 09h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
338 root 4848d 12h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
335 New directory structure. root 4905d 18h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
319 Latest Ethernet IP core testbench. tadejm 6714d 11h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
311 Update script for running different file list files for different RAM models. tadejm 6826d 15h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
310 More signals. tadejm 6826d 15h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
309 Update file list files for different RAM models with byte select accessing. tadejm 6826d 15h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 6826d 15h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
295 Few minor changes. tadejm 6940d 14h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
290 Additional checking for FAILED tests added - for ATS. tadejm 6966d 14h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
208 Virtual Silicon RAMs moved to lib directory tadej 7264d 08h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
207 Virtual Silicon RAM support fixed tadej 7264d 08h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
206 Virtual Silicon RAM added to the simulation. mohor 7264d 09h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
176 lists changed to new directory structure mohor 7274d 14h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
175 Script fixed to new dir structure mohor 7274d 14h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
174 Directory keeper mohor 7274d 15h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
173 Keeps the directory mohor 7274d 15h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
172 NCSIM simulation environment added to cvs mohor 7274d 15h /ethmac/trunk/sim/rtl_sim/ncsim_sim/
171 NCSIM simulation environment added. mohor 7274d 15h /ethmac/trunk/sim/rtl_sim/ncsim_sim/

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