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[/] [ethmac] - Rev 368

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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2852d 02h /ethmac
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2915d 00h /ethmac
366 Readded eth_top.v with a deprecation warning olof 3039d 03h /ethmac
365 Whitespace cleanup olof 3040d 03h /ethmac
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3041d 00h /ethmac
363 quartus project files unneback 3041d 09h /ethmac
362 added Makefiles to build project unneback 3041d 09h /ethmac
361 created branch unneback unneback 3041d 09h /ethmac
360 Added partial implementation of the debug register from ORPSoC olof 3042d 08h /ethmac
359 Verilator linting fixes olof 3044d 10h /ethmac
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3046d 00h /ethmac
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3046d 00h /ethmac
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3046d 02h /ethmac
355 Import Julius Baxter's verilator hints from ORPSoC olof 3046d 03h /ethmac
354 Whitespace cleanup olof 3046d 03h /ethmac
353 Inherit fixes for bit width of constants from ORPSoC olof 3048d 05h /ethmac
352 Removed delayed assignments from rtl code olof 3052d 11h /ethmac
351 Turn defines into parameters in eth_cop olof 3061d 00h /ethmac
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3061d 01h /ethmac
349 Make all parameters configurable from top level olof 3062d 02h /ethmac

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