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[/] [ethmac] - Rev 360

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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 4638d 19h /ethmac
359 Verilator linting fixes olof 4640d 21h /ethmac
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4642d 11h /ethmac
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4642d 11h /ethmac
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4642d 13h /ethmac
355 Import Julius Baxter's verilator hints from ORPSoC olof 4642d 14h /ethmac
354 Whitespace cleanup olof 4642d 14h /ethmac
353 Inherit fixes for bit width of constants from ORPSoC olof 4644d 16h /ethmac
352 Removed delayed assignments from rtl code olof 4648d 22h /ethmac
351 Turn defines into parameters in eth_cop olof 4657d 11h /ethmac
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4657d 12h /ethmac
349 Make all parameters configurable from top level olof 4658d 13h /ethmac
348 Added option to dump VCD files olof 4659d 12h /ethmac
347 Added information about running with Icarus Verilog olof 4659d 12h /ethmac
346 Updated project location olof 4659d 14h /ethmac
345 Temporarily disable failing tests olof 4659d 16h /ethmac
344 bit 9 in phy control register is self clearing olof 4665d 18h /ethmac
343 Address miss should not be asserted on short frames olof 4669d 14h /ethmac
342 Added cast to avoid inequality when comparing different data types olof 4669d 14h /ethmac
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4669d 14h /ethmac

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