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[/] [ethmac] - Rev 368

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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 5053d 23h /ethmac
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 5116d 20h /ethmac
366 Readded eth_top.v with a deprecation warning olof 5241d 00h /ethmac
365 Whitespace cleanup olof 5242d 00h /ethmac
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 5242d 21h /ethmac
363 quartus project files unneback 5243d 06h /ethmac
362 added Makefiles to build project unneback 5243d 06h /ethmac
361 created branch unneback unneback 5243d 06h /ethmac
360 Added partial implementation of the debug register from ORPSoC olof 5244d 05h /ethmac
359 Verilator linting fixes olof 5246d 07h /ethmac
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 5247d 21h /ethmac
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 5247d 21h /ethmac
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 5247d 23h /ethmac
355 Import Julius Baxter's verilator hints from ORPSoC olof 5248d 00h /ethmac
354 Whitespace cleanup olof 5248d 00h /ethmac
353 Inherit fixes for bit width of constants from ORPSoC olof 5250d 02h /ethmac
352 Removed delayed assignments from rtl code olof 5254d 07h /ethmac
351 Turn defines into parameters in eth_cop olof 5262d 21h /ethmac
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 5262d 22h /ethmac
349 Make all parameters configurable from top level olof 5263d 22h /ethmac
348 Added option to dump VCD files olof 5264d 21h /ethmac
347 Added information about running with Icarus Verilog olof 5264d 22h /ethmac
346 Updated project location olof 5265d 00h /ethmac
345 Temporarily disable failing tests olof 5265d 02h /ethmac
344 bit 9 in phy control register is self clearing olof 5271d 04h /ethmac
343 Address miss should not be asserted on short frames olof 5275d 00h /ethmac
342 Added cast to avoid inequality when comparing different data types olof 5275d 00h /ethmac
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 5275d 00h /ethmac
340 Don't fail if log dir already exists olof 5275d 22h /ethmac
339 Added basic support for Icarus Verilog olof 5276d 21h /ethmac

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