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Rev Log message Author Age Path
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6679d 06h /
99 Document revised. mohor 6686d 05h /
98 Document revised. mohor 6686d 06h /
97 Small typo fixed. lampret 6703d 04h /
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 6707d 04h /
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 6707d 07h /
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 6707d 07h /
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 6712d 05h /
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 6713d 07h /
91 Comments in Slovene language removed. mohor 6713d 07h /
90 casex changed with case, fifo reset changed. mohor 6713d 07h /
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
changed.
mohor 6717d 05h /
88 rx_fifo was not always cleared ok. Fixed. mohor 6723d 04h /
87 Status was not latched correctly sometimes. Fixed. mohor 6723d 06h /
86 Big Endian problem when sending frames fixed. mohor 6724d 13h /
85 Log info was missing. mohor 6729d 23h /
84 LinkFail signal was not latching appropriate bit. mohor 6729d 23h /
83 MAC address recognition was not correct (bytes swaped). mohor 6729d 23h /
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 6730d 01h /
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 6730d 01h /

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