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Rev Log message Author Age Path
117 Clock mrx_clk set to 2.5 MHz. mohor 7381d 01h /
116 Testing environment also includes traffic cop, memory interface and host
mohor 7381d 01h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7381d 23h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7382d 20h /
113 RxPointer bug fixed. mohor 7389d 12h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7390d 02h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7390d 15h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7390d 18h /
109 Comment removed. mohor 7390d 19h /
108 Testbench supports unaligned accesses. mohor 7458d 04h /
107 TX_BUF_BASE changed. mohor 7458d 04h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7458d 05h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7467d 06h /
104 FCS should not be included in NibbleMinFl. mohor 7469d 00h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7469d 01h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7469d 01h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7469d 01h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7469d 01h /
99 Document revised. mohor 7476d 00h /
98 Document revised. mohor 7476d 00h /

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