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Rev Log message Author Age Path
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 8011d 01h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8011d 01h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8011d 01h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 8011d 02h /
99 Document revised. mohor 8018d 00h /
98 Document revised. mohor 8018d 01h /
97 Small typo fixed. lampret 8034d 23h /
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8038d 23h /
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 8039d 02h /
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 8039d 02h /

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