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Rev Log message Author Age Path
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 6576d 00h /
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 6595d 23h /
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 6595d 23h /
126 InvalidSymbol generation changed. mohor 6595d 23h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 6595d 23h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 6596d 00h /
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 6598d 01h /
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 6598d 01h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 6598d 01h /
120 Unused files removed. mohor 6598d 02h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 6598d 02h /
118 ShiftEnded synchronization changed. mohor 6601d 17h /
117 Clock mrx_clk set to 2.5 MHz. mohor 6602d 03h /
116 Testing environment also includes traffic cop, memory interface and host
mohor 6602d 03h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6603d 01h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6603d 23h /
113 RxPointer bug fixed. mohor 6610d 14h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6611d 04h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 6611d 17h /
110 m_wb_cyc_o signal released after every single transfer. mohor 6611d 21h /
109 Comment removed. mohor 6611d 21h /
108 Testbench supports unaligned accesses. mohor 6679d 07h /
107 TX_BUF_BASE changed. mohor 6679d 07h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6679d 07h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6688d 09h /
104 FCS should not be included in NibbleMinFl. mohor 6690d 02h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6690d 03h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6690d 03h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6690d 04h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6690d 04h /

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