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Rev	Log message	Author	Age	Path
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7922d 14h	/
128	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7942d 12h	/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7942d 12h	/
126	InvalidSymbol generation changed.	mohor	7942d 13h	/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7942d 13h	/
124	Define ETH_MIIMODER_RST corrected to 0x00000400.	mohor	7942d 14h	/
123	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7944d 14h	/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7944d 14h	/
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	7944d 14h	/
120	Unused files removed.	mohor	7944d 15h	/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7944d 15h	/
118	ShiftEnded synchronization changed.	mohor	7948d 06h	/
117	Clock mrx_clk set to 2.5 MHz.	mohor	7948d 17h	/
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	7948d 17h	/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7949d 15h	/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7950d 12h	/
113	RxPointer bug fixed.	mohor	7957d 04h	/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7957d 18h	/
111	Master state machine had a bug when switching from master write to master read.	mohor	7958d 07h	/
110	m_wb_cyc_o signal released after every single transfer.	mohor	7958d 10h	/

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[/] - Rev 129

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