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Rev Log message Author Age Path
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 7897d 06h /
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7897d 07h /
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7917d 06h /
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7917d 06h /
126 InvalidSymbol generation changed. mohor 7917d 06h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7917d 06h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7917d 07h /
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7919d 07h /
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7919d 07h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7919d 07h /

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