Subversion Repositories ethmac

[/] - Rev 177


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
177 Bug in MIIM fixed. mohor 7451d 08h /
176 lists changed to new directory structure mohor 7451d 10h /
175 Script fixed to new dir structure mohor 7451d 10h /
174 Directory keeper mohor 7451d 10h /
173 Keeps the directory mohor 7451d 10h /
172 NCSIM simulation environment added to cvs mohor 7451d 10h /
171 NCSIM simulation environment added. mohor 7451d 10h /
170 Headers changed. mohor 7451d 10h /
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7451d 11h /
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7452d 08h /
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7453d 08h /
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7454d 09h /
165 HASH improvement needed. mohor 7454d 12h /
164 Ethernet debug registers removed. mohor 7454d 12h /
163 Another temporary version. Core is almost finished. Testbench not included,
mohor 7455d 04h /
162 Another temporary version. Core is almost finished. Testbench not included,
mohor 7455d 04h /
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7455d 10h /
160 error acknowledge cycle termination added to display. mohor 7455d 10h /
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7456d 06h /
158 Typo fixed. mohor 7456d 07h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.