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163 Another temporary version. Core is almost finished. Testbench not included,
yet"
mohor 7892d 00h /
162 Another temporary version. Core is almost finished. Testbench not included,
yet.
mohor 7892d 00h /
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7892d 05h /
160 error acknowledge cycle termination added to display. mohor 7892d 05h /
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7893d 02h /
158 Typo fixed. mohor 7893d 02h /
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7895d 07h /
156 Valid testbench. mohor 7895d 07h /
155 Minor changes. mohor 7895d 07h /
154 Design document is still under construction. mohor 7896d 07h /

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