OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 190

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
190 Several information added to the file. mohor 7889d 23h /
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7889d 23h /
188 PHY changed. tadej 7890d 20h /
187 _info file added. mohor 7890d 20h /
186 Macro for testbench (DO file). mohor 7890d 21h /
185 Directory keeper. mohor 7890d 21h /
184 Modelsim simulation environment should be ready now. mohor 7890d 21h /
183 Modelsim environment added. mohor 7890d 21h /
182 Full duplex test improved. tadej 7891d 22h /
181 MIIM test look better. mohor 7892d 01h /
180 Bench outputs data to display every 128 bytes. mohor 7894d 20h /
179 Beautiful tests merget together mohor 7894d 21h /
178 Rearanged testcases mohor 7894d 21h /
177 Bug in MIIM fixed. mohor 7895d 01h /
176 lists changed to new directory structure mohor 7895d 03h /
175 Script fixed to new dir structure mohor 7895d 03h /
174 Directory keeper mohor 7895d 03h /
173 Keeps the directory mohor 7895d 03h /
172 NCSIM simulation environment added to cvs mohor 7895d 03h /
171 NCSIM simulation environment added. mohor 7895d 03h /
170 Headers changed. mohor 7895d 03h /
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7895d 04h /
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7896d 01h /
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7897d 01h /
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7898d 02h /
165 HASH improvement needed. mohor 7898d 05h /
164 Ethernet debug registers removed. mohor 7898d 05h /
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7898d 21h /
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7898d 21h /
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7899d 03h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.