URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 221

Rev	Log message	Author	Age	Path
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7854d 21h	/
220	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7857d 22h	/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7857d 22h	/
218	Typo error fixed. (When using Bist)	mohor	7858d 00h	/
217	Bist supported.	mohor	7858d 00h	/
216	Bist signals added.	mohor	7858d 00h	/
215	Bist supported.	mohor	7858d 01h	/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7858d 20h	/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7858d 20h	/
212	Minor $display change.	mohor	7858d 21h	/
211	Bist added.	mohor	7858d 21h	/
210	BIST added.	mohor	7858d 21h	/
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	7860d 00h	/
208	Virtual Silicon RAMs moved to lib directory	tadej	7875d 18h	/
207	Virtual Silicon RAM support fixed	tadej	7875d 18h	/
206	Virtual Silicon RAM added to the simulation.	mohor	7875d 18h	/
205	ETH_VIRTUAL_SILICON_RAM supported.	mohor	7875d 19h	/
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7875d 19h	/
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7875d 19h	/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7878d 20h	/