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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6182d 17h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6185d 17h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6185d 17h /
218 Typo error fixed. (When using Bist) mohor 6185d 19h /
217 Bist supported. mohor 6185d 19h /
216 Bist signals added. mohor 6185d 19h /
215 Bist supported. mohor 6185d 20h /
214 Signals for WISHBONE B3 compliant interface added. mohor 6186d 16h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6186d 16h /
212 Minor $display change. mohor 6186d 16h /
211 Bist added. mohor 6186d 16h /
210 BIST added. mohor 6186d 16h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6187d 19h /
208 Virtual Silicon RAMs moved to lib directory tadej 6203d 13h /
207 Virtual Silicon RAM support fixed tadej 6203d 14h /
206 Virtual Silicon RAM added to the simulation. mohor 6203d 14h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6203d 14h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6203d 14h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6203d 14h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6206d 16h /

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