OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 228

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7853d 02h /
227 Changed BIST scan signals. tadejm 7853d 02h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7853d 03h /
225 Some minor changes. tadejm 7853d 03h /
224 Signals for a wave window in Modelsim. tadejm 7853d 05h /
223 Some code changed due to bug fixes. tadejm 7853d 05h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7857d 03h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7857d 03h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7860d 03h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7860d 03h /
218 Typo error fixed. (When using Bist) mohor 7860d 05h /
217 Bist supported. mohor 7860d 05h /
216 Bist signals added. mohor 7860d 05h /
215 Bist supported. mohor 7860d 06h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7861d 02h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7861d 02h /
212 Minor $display change. mohor 7861d 02h /
211 Bist added. mohor 7861d 02h /
210 BIST added. mohor 7861d 02h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7862d 05h /
208 Virtual Silicon RAMs moved to lib directory tadej 7877d 23h /
207 Virtual Silicon RAM support fixed tadej 7877d 23h /
206 Virtual Silicon RAM added to the simulation. mohor 7878d 00h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7878d 00h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7878d 00h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7878d 00h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7881d 01h /
201 Core size added to the document. mohor 7881d 02h /
200 File with lower case checked in instead. mohor 7881d 02h /
199 Datasheet name changed to lower case name. mohor 7881d 02h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.