OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 236

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6466d 15h /
235 rev 4. mohor 6467d 06h /
234 Figure list assed to the revision 3. mohor 6467d 14h /
233 Revision 0.3 released. Some figures added. mohor 6467d 14h /
232 fpga define added. mohor 6472d 09h /
231 Description of Core Modules added (figure). mohor 6474d 10h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6478d 07h /
229 case changed to casex. mohor 6478d 07h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6478d 11h /
227 Changed BIST scan signals. tadejm 6478d 11h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6478d 12h /
225 Some minor changes. tadejm 6478d 12h /
224 Signals for a wave window in Modelsim. tadejm 6478d 14h /
223 Some code changed due to bug fixes. tadejm 6478d 14h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6482d 12h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6482d 12h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6485d 12h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6485d 12h /
218 Typo error fixed. (When using Bist) mohor 6485d 14h /
217 Bist supported. mohor 6485d 14h /
216 Bist signals added. mohor 6485d 14h /
215 Bist supported. mohor 6485d 15h /
214 Signals for WISHBONE B3 compliant interface added. mohor 6486d 11h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6486d 11h /
212 Minor $display change. mohor 6486d 11h /
211 Bist added. mohor 6486d 11h /
210 BIST added. mohor 6486d 11h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6487d 15h /
208 Virtual Silicon RAMs moved to lib directory tadej 6503d 08h /
207 Virtual Silicon RAM support fixed tadej 6503d 09h /

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.