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Rev	Log message	Author	Age	Path
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7828d 11h	/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7828d 12h	/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7828d 12h	/
238	Defines fixed to use generic RAM by default.	mohor	7840d 16h	/
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7842d 21h	/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7842d 21h	/
235	rev 4.	mohor	7843d 12h	/
234	Figure list assed to the revision 3.	mohor	7843d 20h	/
233	Revision 0.3 released. Some figures added.	mohor	7843d 20h	/
232	fpga define added.	mohor	7848d 15h	/
231	Description of Core Modules added (figure).	mohor	7850d 16h	/
230	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7854d 13h	/
229	case changed to casex.	mohor	7854d 13h	/
228	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7854d 17h	/
227	Changed BIST scan signals.	tadejm	7854d 17h	/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7854d 18h	/
225	Some minor changes.	tadejm	7854d 18h	/
224	Signals for a wave window in Modelsim.	tadejm	7854d 20h	/
223	Some code changed due to bug fixes.	tadejm	7854d 20h	/
222	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7858d 18h	/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7858d 18h	/
220	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7861d 18h	/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7861d 18h	/
218	Typo error fixed. (When using Bist)	mohor	7861d 20h	/
217	Bist supported.	mohor	7861d 20h	/
216	Bist signals added.	mohor	7861d 20h	/
215	Bist supported.	mohor	7861d 21h	/
214	Signals for WISHBONE B3 compliant interface added.	mohor	7862d 17h	/
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7862d 17h	/
212	Minor $display change.	mohor	7862d 17h	/

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[/] - Rev 241

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