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248 wb_rst_i is used for MIIM reset. mohor 6439d 16h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 6442d 20h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6442d 20h /
245 Rev 1.7. mohor 6443d 13h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6443d 15h /
243 Late collision is not reported any more. tadejm 6443d 21h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6444d 11h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6444d 12h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6444d 12h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6444d 12h /
238 Defines fixed to use generic RAM by default. mohor 6456d 16h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6458d 21h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6458d 21h /
235 rev 4. mohor 6459d 12h /
234 Figure list assed to the revision 3. mohor 6459d 20h /
233 Revision 0.3 released. Some figures added. mohor 6459d 20h /
232 fpga define added. mohor 6464d 15h /
231 Description of Core Modules added (figure). mohor 6466d 16h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6470d 13h /
229 case changed to casex. mohor 6470d 13h /

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