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249 This commit was manufactured by cvs2svn to create tag 'rel_11'. 6523d 12h /
248 wb_rst_i is used for MIIM reset. mohor 6523d 12h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 6526d 15h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 6526d 15h /
245 Rev 1.7. mohor 6527d 08h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 6527d 11h /
243 Late collision is not reported any more. tadejm 6527d 16h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 6528d 07h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 6528d 07h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 6528d 07h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 6528d 07h /
238 Defines fixed to use generic RAM by default. mohor 6540d 11h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6542d 16h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6542d 16h /
235 rev 4. mohor 6543d 07h /
234 Figure list assed to the revision 3. mohor 6543d 15h /
233 Revision 0.3 released. Some figures added. mohor 6543d 15h /
232 fpga define added. mohor 6548d 10h /
231 Description of Core Modules added (figure). mohor 6550d 12h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6554d 08h /
229 case changed to casex. mohor 6554d 08h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6554d 12h /
227 Changed BIST scan signals. tadejm 6554d 12h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6554d 14h /
225 Some minor changes. tadejm 6554d 14h /
224 Signals for a wave window in Modelsim. tadejm 6554d 15h /
223 Some code changed due to bug fixes. tadejm 6554d 15h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6558d 13h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6558d 13h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6561d 14h /

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