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Rev Log message Author Age Path
346 Updated project location olof 4891d 11h /
345 Temporarily disable failing tests olof 4891d 13h /
344 bit 9 in phy control register is self clearing olof 4897d 15h /
343 Address miss should not be asserted on short frames olof 4901d 11h /
342 Added cast to avoid inequality when comparing different data types olof 4901d 11h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4901d 11h /
340 Don't fail if log dir already exists olof 4902d 09h /
339 Added basic support for Icarus Verilog olof 4903d 08h /
338 root 5695d 14h /
337 root 5751d 16h /
336 Added old uploaded documents to new repository. root 5752d 19h /
335 New directory structure. root 5752d 19h /
334 Minor fixes for Icarus simulator. igorm 7200d 21h /
333 Some small fixes + some troubles fixed. igorm 7201d 09h /
332 Case statement improved for synthesys. igorm 7214d 14h /
331 Tests for delayed CRC and defer indication added. igorm 7229d 16h /
330 Warning fixes. igorm 7229d 16h /
329 Defer indication fixed. igorm 7229d 17h /
328 Delayed CRC fixed. igorm 7229d 18h /
327 Defer indication fixed. igorm 7229d 18h /

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