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Rev Log message Author Age Path
346 Updated project location olof 4086d 20h /
345 Temporarily disable failing tests olof 4086d 21h /
344 bit 9 in phy control register is self clearing olof 4092d 23h /
343 Address miss should not be asserted on short frames olof 4096d 19h /
342 Added cast to avoid inequality when comparing different data types olof 4096d 19h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4096d 20h /
340 Don't fail if log dir already exists olof 4097d 17h /
339 Added basic support for Icarus Verilog olof 4098d 16h /
338 root 4890d 22h /
337 root 4947d 00h /
336 Added old uploaded documents to new repository. root 4948d 03h /
335 New directory structure. root 4948d 03h /
334 Minor fixes for Icarus simulator. igorm 6396d 05h /
333 Some small fixes + some troubles fixed. igorm 6396d 17h /
332 Case statement improved for synthesys. igorm 6409d 23h /
331 Tests for delayed CRC and defer indication added. igorm 6425d 00h /
330 Warning fixes. igorm 6425d 01h /
329 Defer indication fixed. igorm 6425d 02h /
328 Delayed CRC fixed. igorm 6425d 02h /
327 Defer indication fixed. igorm 6425d 02h /

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