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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3406d 01h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 3406d 02h /
354 Whitespace cleanup olof 3406d 02h /
353 Inherit fixes for bit width of constants from ORPSoC olof 3408d 04h /
352 Removed delayed assignments from rtl code olof 3412d 09h /
351 Turn defines into parameters in eth_cop olof 3420d 23h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3421d 00h /
349 Make all parameters configurable from top level olof 3422d 01h /
348 Added option to dump VCD files olof 3422d 23h /
347 Added information about running with Icarus Verilog olof 3423d 00h /
346 Updated project location olof 3423d 02h /
345 Temporarily disable failing tests olof 3423d 04h /
344 bit 9 in phy control register is self clearing olof 3429d 06h /
343 Address miss should not be asserted on short frames olof 3433d 02h /
342 Added cast to avoid inequality when comparing different data types olof 3433d 02h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3433d 02h /
340 Don't fail if log dir already exists olof 3434d 00h /
339 Added basic support for Icarus Verilog olof 3434d 23h /
338 root 4227d 05h /
337 root 4283d 07h /

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